Collected sources and patterns will appear here. Add from search, explore, or the patterns library.
L1CacheMiss -> CoherentMemoryResponse
Maintain memory coherence across diverse tile-specific L1 caches (vector, stencil, scalar) via a directory tracking system hosted at shared L2 cache slices.
Problem it solves
Domain-specific tiles with custom L1 configurations can cause memory inconsistency if they access shared physical memory simultaneously.
Consumes
Emits
The real projects this mechanism was found in. Attribution is the point — this is how the best teams actually do it.