Collected sources and patterns will appear here. Add from search, explore, or the patterns library.
InstructionStream -> Tuple<ScalarOp, VectorOp>
Split incoming RISC-V instruction streams into parallel scalar execution pipelines and decoupled vector queues to overlap address generation with vector math.
Problem it solves
Vector execution latency stalls the main instruction pipeline if scalar and vector execution are strictly lock-stepped.
Consumes
Emits
The real projects this mechanism was found in. Attribution is the point — this is how the best teams actually do it.