Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit - A P-Bit

This project represents high-moat 'deep tech' research. While the GitHub metrics (0 stars, 5 forks) reflect a very new release, the 5 forks within 3 days indicate significant academic/specialized interest. The defensibility is high because the work requires physical semiconductor fabrication capabilities, deep expertise in spintronics, and CMOS integration—it cannot be replicated by software engineers or frontier labs focusing on LLM scaling. The 3T-1MTJ architecture is a specific optimization over larger p-bit designs, offering better density and power efficiency. Frontier risk is low because entities like OpenAI or Anthropic are hardware-agnostic at the circuit level, though they may eventually consume the resulting chips. The primary competitors are academic labs (e.g., Purdue, Tohoku University) and specialized hardware startups (e.g., Lucid Circuit). The displacement horizon is long (3+ years) because moving from an experimental demonstration to a commercial-grade Ising machine or probabilistic processor requires extensive hardware maturation and supply chain integration.