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(RTLState, ReferenceISSState) -> VerificationStatus
Execute an instruction stream concurrently on an RTL design and an Instruction Set Simulator (ISS) reference model, comparing architectural state updates at each instruction retirement.
Problem it solves
Post-execution trace debugging fails to isolate the exact instruction or cycle where hardware state diverged from the instruction set architecture standard.
Consumes
Emits
The real projects this mechanism was found in. Attribution is the point — this is how the best teams actually do it.