EPAC: The Last Dance

EPAC (European Processor Accelerator) represents a significant multi-year sovereign silicon effort by the European Processor Initiative (EPI). Its defensibility score of 8 is derived from the immense physical and capital barriers to entry inherent in custom silicon development (tape-out on GF22FDX, 0.3B transistors). This is not a software project that can be easily cloned; it is a validated hardware implementation involving multiple partners like BSC, ETH Zurich, and Semidynamics. While the 22nm node is trailing-edge compared to consumer 3nm/5nm chips, the moat lies in the domain-specific architecture (VEC and Stencil tiles) and the geopolitical mandate for European technological sovereignty. Frontier labs (OpenAI/Google) pose low risk here as they focus on general-purpose AI accelerators (TPUs/LPUs) or massive-scale cloud infrastructure, rather than specialized RISC-V HPC chips for European research clusters. The 39 forks in just 3 days for an academic/hardware project indicate high interest within the RISC-V and HPC research communities. The main risk is the competitive gap in raw TFLOPS compared to commercial giants like NVIDIA or AMD, but within its niche of sovereign, energy-efficient HPC, it is category-defining for the region.