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A collection of hardware acceleration IP cores and reference designs implemented using Vitis High-Level Synthesis (HLS) for Xilinx UltraScale+ FPGAs, targeting low-latency DSP, 5G, and HFT applications.
stars
11
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4
The project is a personal portfolio or educational repository of HLS designs. While it addresses high-value niches like HFT and 5G, the low star count and lack of velocity suggest it is a set of learning examples or small-scale IP blocks rather than a robust, industry-standard library. It is easily reproducible by hardware engineers using standard Vitis HLS optimization patterns.
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reference_implementation
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