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A hardware-level CNN accelerator implemented in RTL for the PYNQ Z2 FPGA, optimized for low-power INT8 object detection inference.
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The project is a specialized hardware implementation for a specific FPGA board (PYNQ Z2), likely created for a competition (Bharat AI Challenge). While hardware RTL work requires more effort than a simple software wrapper, the lack of stars, forks, or documentation beyond the competition context suggests it is a personal/educational experiment. Frontier labs do not compete in the niche of low-end FPGA RTL design for legacy Zynq chips.
TECH STACK
INTEGRATION
hardware_dependent
READINESS