DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining

DRsam is an academic research project addressing a niche but critical gap in RISC-V security. While most side-channel detection focuses on x86/ARM, this project targets the emerging RISC-V ecosystem. The defensibility is low (2/10) because the repository currently lacks community stars and represents a static reference implementation for a paper rather than a maintained tool. Its moat is purely academic/technical expertise in hardware performance counters (HPCs). Frontier labs (OpenAI/Google) are unlikely to compete here as it's too deep in the hardware stack, but RISC-V vendors (e.g., SiFive, Ventana) or security-focused hypervisor developers are the natural owners of this capability. The project is valuable as an exploratory technique—using Association Rule Mining instead of traditional deep learning—to reduce the overhead of attack detection, but it is highly likely to be superseded by hardware-level mitigations or more robust kernel-integrated monitoring tools within 1-2 years.