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A dual-core RISC-V SoC architecture designed using High-Level Synthesis (HLS) for FPGAs, featuring a Network-on-Chip (NoC) interconnect for memory management and an integrated AI accelerator.
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The project combines several advanced hardware architecture concepts (NoC, multi-core RISC-V, HLS-based AI acceleration) into a single system. While technically complex to implement, the project has zero traction (0 stars/forks) and serves as a personal or academic experiment. It lacks a community or unique IP that would make it defensible against similar academic or industry projects.
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