Collected molecules will appear here. Add from search or explore.
An FPGA-based hardware accelerator implementing a 4×4 systolic array architecture for matrix multiplication, featuring tiling support for larger matrices (up to 64×64) and a UVM-based verification environment.
stars
3
forks
3
The project is a standard implementation of a systolic array, a well-documented hardware architecture used in TPUs and NPUs. With only 3 stars and no recent activity, it serves primarily as an educational or personal reference implementation rather than a production-grade IP core or a project with a defensible moat.
TECH STACK
INTEGRATION
reference_implementation
READINESS