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Translates a subset of Python code into synthesizable Verilog HDL for hardware design on FPGAs and ASICs.
stars
110
forks
10
Polyphony tackles the technically complex challenge of High-Level Synthesis (HLS) from Python. While the domain has high barriers to entry, the project has low adoption (110 stars) and stagnant development velocity over a 10-year period. It competes in a niche occupied by more established tools like MyHDL or vendor-specific C-based HLS tools. Frontier labs are unlikely to enter this niche space directly.
TECH STACK
INTEGRATION
cli_tool
READINESS