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FPGA-based hardware acceleration of the AlexNet convolutional neural network using Xilinx Vivado High Level Synthesis (HLS).
Defensibility
stars
21
forks
12
The project is a legacy academic/tutorial implementation of AlexNet on FPGA. With only 21 stars over nearly 3,000 days, it lacks any significant adoption or community momentum. AlexNet is a 2012-era architecture that has been rendered obsolete by modern models like ResNet, EfficientNet, and Vision Transformers (ViTs). From a competitive standpoint, this repository offers no unique IP or optimization that isn't surpassed by modern automated toolchains like Xilinx Vitis AI, Apache TVM (VTA), or hls4ml. The low fork/star count and zero velocity indicate it is a 'frozen' project, likely used for a single research paper or course. Frontier labs have zero interest in AlexNet hardware acceleration, and the platform risk is low only because the technology is too niche and dated for a major platform to bother absorbing it. It serves only as a historical reference for how HLS was applied to CNNs in the mid-2010s.
TECH STACK
INTEGRATION
reference_implementation
READINESS